U.SANGEETHA used. The main aim of this review

U.SANGEETHA

M.TECH VLSI IN SATHYABAMA INSTITUTE OF SCIENCE AND
TECHNOLOGY

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(DEEMED TO BE UNIVERSITY),CHENNAI.

[email protected]

ABSTRACT
— This paper is mainly focused on the
detail review and analysis on the application of Vedic maths especially Vedic
multiplier in recent trends. The multiplication plays a important role in
designing and digital application. Here comes Vedic multiplication method which
improves computational skills and also resolve complex problems arises in
normal mathematical multiplication. The advancement of transistor uses Vedic
multiplier process to make low power and high speed system consumes low power
with extension of time delay in latest application. The overall view of this
paper makes us to understand all possible applications of the vedic maths in advance
electronic application.

KEYWORDS:
Vedic Multiplier, CMOS technology, VLSI
application.

 

                                                                                                                                                                             
I.           
INTRODUCTION

Based on Moore’s
law every electronic system will integrated in that same area for every18
months so this review is made on that principle that already existing process
of Vedic Maths is used in most advance method as discussed in various papers.
Vedic multiplication is not only for solving multiplier application but also
used for analyzing power and delay of CMOS multiplier. Here some paper uses
DADDA and ECRL methodology 1. Other methods like Quantum Dot
process for carry save adder 2.

The power and
delay analysis based on the Vedic Multiplication process uses the Verilog
programming 3 method and also some bit multipliers are used.

The main aim of
this review is to find the Vedic multiplication in CMOS system to obtain a
optimized system with less power consumption and more efficient machine .

 

                                                                                                                                                             
II.           
LITREATURE
SURVEY

 

H.V.RAVISH
ARADHYA (2016) has described the design and performance comparison of Adiabatic
8-bit multipliers. Here adiabatic logic is used which makes the design of
promising low power VLSI technologies based on the expenses of the delay. In a
digital system the fundamental blocks are made to contribute the significance
power dissipation and propagation delay. Multipliers are mainly used in DSP
(digital signal processing) and in Image Processing system. The proposed work
of this paper is based on the ECRL based 8-bit multiplier design which is then
compared with the CMOS design.

Wallace-Dadda hybrid multiplier which uses Decomposition Logic to reduce
the carry propagation delay is considered to be the reference design. The Dadda
multiplier and the Vedic multipliers are used as a power optimized designs in
practical. . Hspice is used to obtain the power and delay values of the designed
multipliers in CMOS and ECRL. 8-bit Vedic multiplier provides a power reduction
of about 19.3% as compared to Wallace-Dadda hybrid multiplier. Also the ECRL
designs uses 77% less power as compared to the CMOS design .Hence the proposed
paper uses 8-bit Vedic multiplier with ECRL design.

Hence the proposed paper work is used for the applications of medical
electronics and wireless sensor networks which uses less power which replaces
Dadda hybrid as a 8-bit vedic multiplier.

Ashvin Chudasama
and Trailokya Nath Sasamal (2016) were proposed the implementation 4×4 Vedic
multiplier using carry save adder in Quantum dot cellular (QCA)  automata which explains that multiplier is the
basic structural logic used in DSP, ALU and the communication systems. QCA is a
alternative method implement the small size design and the low power
consumptions. In this paper they proposed the 4-bit Vedic multiplier ( uses
Urdhva Tiryagbhyam sutra) design using QCA technology.

The
partial product addition in Vedic multiplication is realized using the carry
save adder.The simulation is made using QCA design tool and which is proved to
be more efficient. The simulation results in reduction of 30% cell count ,
60%  reduction in area and  50% delay reduction as compared to 4×4
Wallace Dadda technology.

This
paper is applied directly in low power consumption designs and advantage in
efficient power application.

Raj
Kumari and Rajesh Mehra (2016) were described the Power and Delay analysis of
CMOS multipliers in  Vedic algorithm. The
multiplier design is made using 45nm technology for the Vedic algorithm named
as Urdhva-Tiryyagbhyam Sutra. They explains that the effective digital system
design is made based on the high speed , reduced delay , reduced area and the
low power consumption multiplier designs. The 45nm technology design in this
paper uses the backend software tool named as Cadence Virtuoso. Mainly the
multiplier is used for the purpose of carry skip addition methodology. Here the
2-bit multiplier is used which consumes a very low power 5.5489xlO -I watt and
delay of 1.924xlO -12 sec and 4bBit multiplier consumes power of 0.0002854 watt
and delay of 2.0873xlO-7 sec.

Ancient
Vedic multiplication is carried out in the 45nm technology process with reduced
chip area in efficient method. This is the very fastest method of multiplier as
compared to various multipliers which consumes very less power.

L.Sriraman
and T.N.Prabakar (2012) proposed the design and implementation of two variable
multiplier using KCM and Vedic mathematics. In this paper, a novel multiplier architecture based
on ROM approach using Vedic Mathematics is proposed. As we analyses in the
previous paper of review here also the same Urdhva-Tiryyagbhyam was used. This
architecture is same as that of the KCM multiplier but the KCM had one constant
and one input but here there are two variables are used for multiplication.
Here the cyclone III FPGA architecture is used for designing hence this model
is 1.5 times faster than all the other multipliers for 16×16 case and consumes
76% less area for 8×8 multipliers and 42% area for 16×16 multipliers.

Hence
this proposed model has higher performance for high bit multiplication. In this
proposed system the higher order bit multiplications are realized using lower
bit order multiplication. This is due to memory constraints and so effective
memory implementation and deployment of memory compression algorithm can yield
even better results.

Satyendra
tripathi ashutosh kumar singh (2015) has proposed a paper high speed and area
efficient discrete wavelet transform using Vedic multiplier. He discussed that
multiplier is a key factor in arithmetic operation and digital signal
processing algorithm with high speed and alos with less area usage. Multiplier
forma an integral part of processor design. Multiplier consumes more time for
execution and in the other hand image processing and digital signal processing
needs multiplication. Multiplier needs to be designed for wavelet transforms
which posses less area and provide high speed performance. These design reduced hard complexity,
throughput rate and different input/output data format to match different
application needs. The implantation of this proposed design used Spartan 3 FPGA
tool. This model of compressed multiplier provides the least amount of Maximum
Combinational Path Delay (MCPD) and it occupies least areas due to the reduced
number of slices.

 

                                                                                                                                                                            
III.           
CONCLUSION

This literature review creates the new way of
exposure to the Vedic multiplier in latest VLSI and Digital systems and also
creates awareness about the importance of Multiplication in digital and image
processing system. All papers discussed above are based on Vedic multiplier and
their usage in different field of technology. Various implementation tools are
used in the papers for the realization of the multiplication using optimized
technique. Overall review gives me some idea to use the Vedic multiplication in
VLSI technology .Multiplier based on Vedic maths need to be designed based  on the usage of less chip area , high speed
and more efficient processor to be satisfied with the Moore’s law of designing.

 

                                                                                                                                                                           
IV.           
REFERENCES

 

1  
H.V.RAVISH ARADHYA (2016),  “The design and performance comparison of
Adiabatic 8-bit multipliers”, IEEE Conference, Bangalore .

2  
Ashvin Chudasama and Trailokya Nath
Sasamal (2016), “Implementation 4×4 Vedic multiplier using carry save adder in
Quantum dot cellular (QCA)  automata
which explains that multiplier, International Conference on Communication and
Signal Processing, April 6-8, 2016, India.

3  
Raj Kumari and Rajesh Mehra (2016), ”
Power and Delay analysis of CMOS multipliers in 
Vedic algorithm”, 1st IEEE International Conference on Power
Electronics. Intelligent Control and Energy Systems (ICPEICES-2016).

4  
L.Sriraman and T.N.Prabakar (2012), “Design
and implementation of two variable multiplier using KCM and Vedic mathematics”,
1″ In!’ I Conf. on Recent Advances in Information Technology  (RAIT -2012 ).

5  
Satyendra tripathi ashutosh kumar singh
(2015), “High speed and area efficient discrete wavelet transform using Vedic
multiplier”, 2015 International Conference on Computational Intelligence and
Communication Networks.

6  
S.G. Mallat, “A Theory for
Multiresolution Signal Decomposition: The Wavelet Representation”, IEEE Trans.
on Pattern Analysis on Machine Intelligence, 110. July1989, pp. 674-693.