System Integrity Protection Schemes (SIPS) are developed to protect the integrity of the power system when it undergoes severe disturbances, as a last resort to prevent cascading events and blackouts. The integration of Power Electronics (PE) devices has brought increased level of risks and uncertainties to secure and stable operation of power systems. The increased amount of asynchronously connected generation affects power system inertia and fault level. These are directly linked to the efficacy of existing SIPS.
There are many different types of SIPS being used in power systems around the globe, such as under-frequency load shedding (UFLS), under-voltage load shedding (UVLS) and power swing tripping (PST) schemes. Logically, SIPS perform optimally only if they operate under conditions and PE penetration level for which they are essentially designed. Extensive simulation studies would demonstrate that an increase or decrease in PE penetration level would undermine the performance of SIPS installed. The conclusions obtained from such studies can be outlined as below
· Overshedding is a potential problem when the UFLS relays are set based on a lower PE penetration level than the actual PE penetration level.
· Reaching lower frequency nadirs and falling under the impermissible frequency 47.5 Hz become quite likely when the inertia time constant of the system is small.
· Power factor control mode, as the most practiced mode on PE devices, results in very fast developing voltage instabilities. This could lead to voltage collapse in many cases as conventional UVLS relays may fail to respond sufficiently fast.
· The increased rate of change of impedance and unexpected impedance trajectories due to increasing PE penetration levels are the biggest challenge for traditional impedance-based PST schemes.
· System transient stability cannot be maintained under high PE penetrations, since PST relays may more frequently fail to separate the system as planned.
The problems outlined above help develop several ideas to improve SIPS performance under increasing PE penetration levels. These include, but are not limited to, the use of additional local variables as input to SIPS relays, real time estimation of the system inertia and fault level, and resorting to Synchronized Measurement Technologies.